? semiconductor components industries, llc, 2013 october, 2013 ? rev. 1 1 publication order number: nb3n51034/d nb3n51034 3.3v, crystal to 100mhz/ 200mhz quad hcsl/lvds clock generator the nb3n51034 is a high precision, low phase noise clock generator that supports spread spectrum desi gned for pci express applications. this device takes a 25 mhz fundamental mode parallel resonant crystal and generates 4 differential hcsl/lvds outputs at 100 mhz or 200 mhz (see figure 6 for lvds interface). the nb3n51034 provides selectable spread options of ? 0.5%, ? 1.0%, ? 1.5%, for applications demanding low electromagnetic interfe rence (emi). no spread setting is also available. features ? uses 25 mhz fundamental mode parallel resonant crystal ? power down mode ? 4 low skew hcsl or lvds outputs ? oe tri ? states outputs ? spread of ? 0.5%, ? 1.0%, ? 1.5% and no spread ? pcie gen 1, 2, 3 jitter compliant ? phase noise (ss off) @ 100 mhz: offset noise power 100 hz ? 110 dbc/hz 1 khz ? 123 dbc/hz 10 khz ? 134 dbc/hz 100 khz ? 137 dbc/hz 1 mhz ? 138 dbc/hz 10 mhz ? 154 dbc/hz ? operating range 3.3 v 5% ? industrial t emperature range ? 40 c to +85 c ? functionally compatible with idt557 ? 05, idt5v41066, idt5v41236 ? these are pb ? free devices applications ? networking ? consumer ? computing and peripherals ? industrial equipment ? pcie clock generation gen i, gen ii and gen iii end products ? switch and router ? set top box, lcd tv ? servers, desktop computers ? automated test equipment figure 1. nb3n51034 simplified logic diagram phase detector charge pump n clock buffer crystal oscillator clk2 clk2 x1/clk x2 vco 25 mhz clock or crystal gnd vdd s0 s1 oe iref hcsl output clk3 clk3 hcsl output clk0 clk0 hcsl output clk1 clk1 hcsl output s2 pd spread spectrum circuit marking diagram tssop ? 20 dt suffix case 948e http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) nb3n 1034 alyw
nb3n51034 http://onsemi.com 2 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 vddxd s0 s1 s2 x1/clk x2 oe clk0 clk1 gndoda clk0 figure 2. pin configuration (top view) vddoda 912 gndxd 10 11 iref clk1 clk2 clk3 clk2 clk3 pd table 1. pin description pin symbol i/o description 1 vddxd power connect to a +3.3 v source. 2 s0 input spread spectrum select pin 0. see spread spectrum select table. internal pull ? up resistor. 3 s1 input spread spectrum select pin 1. see spread spectrum select table. internal pull ? up resistor. 4 s2 input spread spectrum select pin 2. see spread spectrum select table. internal pull ? up resistor. 5 x1/clk input crystal interface or single ? ended reference clock input. 6 x2 output crystal interface. float this pin for reference clock input clk. 7 pd input power down. internal pull ? up resistor. 8 oe input output enable. tri ? state output (high=enable outputs, low=disable outputs). internal pull ? up resistor. 9 gndxd power connect to digital circuit ground. 10 i ref output precision resistor attached to this pin is connected to the internal current reference. 11 clk3 output selectable 100/200 mhz spread spectrum differential compliment output clock 3. 12 clk3 output selectable 100/200 mhz spread spectrum differential true output clock 3. 13 clk2 output selectable 100/200 mhz spread spectrum differential compliment output clock 2. 14 clk2 output selectable 100/200 mhz spread spectrum differential true output clock 2. 15 vddoda power connect to a +3.3 v analog source. 16 gndoda power output and analog circuit ground. 17 clk1 output selectable 100/200 mhz spread spectrum differential compliment output clock 1. 18 clk1 output selectable 100/200 mhz spread spectrum differential true output clock 1. 19 clk0 output selectable 100/200 mhz spread spectrum differential compliment output clock 0. 20 clk0 output selectable 100/200 mhz spread spectrum differential true output clock 0. table 2. output frequency and spread spectrum select table s2 s1 s0 spread% spread type output frequency 0 0 0 ? 0.5 down 100 0 0 1 ? 1.0 down 100 0 1 0 ? 1.5 down 100 0 1 1 no spread n/a 100 1 0 0 ? 0.5 down 200 1 0 1 ? 1.0 down 200 1 1 0 ? 1.5 down 200 1 1 1 no spread n/a 200 recommended crystal parameters crystal fundamental at ? cut frequency 25 mhz load capacitance 16 ? 20 pf shunt capacitance, c0 7 pf max equivalent series resistance 50 max initial accuracy at 25 c 20 ppm temperature stability 30 ppm aging 20 ppm
nb3n51034 http://onsemi.com 3 table 3. attributes characteristic value internal input default state resistor (oe, sx, pd ) 110 k esd protection human body model 2 kv moisture sensitivity, indefinite time out of dray pack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 132,000 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v dd positive power supply gnd = 0 v 4.6 v v i input voltage (v in ) gnd = 0 v gnd v i v dd ? 0.5 v to v dd +0.5 v v t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm tssop?20 tssop?20 140 50 c/w c/w jc thermal resistance (junction ? to ? case) (note 3) tssop ? 20 23 to 41 c/w t sol wave solder 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simu ltaneously. if stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power). table 5. dc characteristics (v dd = 3.3 v 5%, gnd = 0 v, t a = ? 40 c to +85 c, note 4) symbol characteristic min typ max unit vdd power supply voltage 3.135 3.3 3.465 v i dd power supply current, 200 mhz output, sson 135 ma i ddoe power supply current when oe is set low 60 ma i ddpd power supply current (pd = low, no load) 1.5 ma v ih input high voltage (x1/clk, s0, s1, s2 and oe) 2000 v dd + 300 mv v il input low voltage (x1/clk, s0, s1, s2 and oe) gnd ? 300 800 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. measurement taken with outputs terminated with r s = 33.2 , r l = 50 , with test load capacitance of 2 pf and current biasing resistor set at 475 . see figure 5. guaranteed by characterization.
nb3n51034 http://onsemi.com 4 table 6. ac characteristics (v dd = 3.3 v 5%, gnd = 0 v, t a = ? 40 c to +85 c; note 5) symbol characteristic min typ max unit f clkin clock/crystal input frequency 25 mhz f clkout output clock frequency 100/200 mhz vmax absolute maximum output voltage (notes 6, 7) 1150 mv vmin absolute minimum output voltage (notes 6, 8) ? 300 mv vrb ringback voltage (notes 9, 10) ? 100 100 mv voh output high voltage (note 6) 660 850 mv vol output low voltage (note 6) ? 150 27 mv v cross absolute crossing voltage (notes 6, 10, 11) 250 550 mv v cross total variation of v cross (notes 6, 10, 12) 140 mv f mod spread spectrum modulation frequency 30 31.5 33.33 khz ssc red spectral reduction (note 13), 3 rd harmonic ? 10 db t skew within device output to output skew 40 ps noise phase ? noise performance ss off f clkout = 100 mhz dbc/hz @ 100 hz offset from carrier ? 110 @ 1 khz offset from carrier ? 123 @ 10 khz offset from carrier ? 134 @ 100 khz offset from carrier ? 137 @ 1 mhz offset from carrier ? 138 @ 10 mhz offset from carrier ? 154 t oe output enable/disable time (all outputs) (note 14) 10 s t duty_cycle output clock duty cycle (measured at cross point) 45 50 55 % t r output risetime (measured from 175 mv to 525 mv, figure 7) 175 340 700 ps t f output falltime (measured from 525 mv to 175 mv, figure 7) 175 400 700 ps t r output risetime variation (single ? ended) 125 ps t f output falltime variation (single ? ended) 125 ps stabilization time stabilization time from powerup v dd = 3.3 v 3.0 ms note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. measurement taken from differential output on single ? ended channel terminated with r s = 33.2 , r l = 50 , with test load capacitance of 2 pf and current biasing resistor set at 475 . see figure 5. guaranteed by characterization. 6. measurement taken from single-ended waveform 7. defined as the maximum instantaneous voltage value including positive overshoot 8. defined as the maximum instantaneous voltage value including negative overshoot 9. measurement taken from differential waveform 10. measured at crossing point where the instantaneous voltage value of the rising edge of clkx+ equals the falling edge of clkx -. 11. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. 12. defined as the total variation of all crossing voltage of rising clkx+ and falling clkx-. this is maximum allowed variance i n the vcross for any particular system. 13. spread spectrum clocking enabled. 14. output pins are tri ? stated when oe is asserted low. output pins are driven differentially when oe is high unless device is in power down mode, pd = low.
nb3n51034 http://onsemi.com 5 table 7. ac electrical characteristics ? pci express jitter specifications , v dd = 3.3 v 5%, t a = ? 40 c to 85 c symbol parameter test conditions min typ max pcie industry spec unit tj (pcie gen 1) phase jitter peak ? to ? peak (notes 16 and 19) f = 100 mhz, 25 mhz crystal input evaluation band: 0 hz ? nyquist (clock frequency/2) ssoff 10 20 86 ps sson ( ? 0.5%) 19 28 trefclk_hf_rms (pcie gen 2) phase jitter rms (notes 17 and 19) f = 100 mhz, 25 mhz crystal input high band: 1.5 mhz ? nyquist (clock frequency/2) ssoff 1.0 1.8 3.1 ps sson ( ? 0.5%) 1.1 1.9 trefclk_lf_rms (pcie gen 2) phase jitter rms (notes 17 and 19) f = 100 mhz, 25 mhz crystal input low band: 10 khz ? 1.5 mhz ssoff 0.1 0.15 3.0 ps sson ( ? 0.5%) 0.8 1.1 trefclk_rms (pcie gen 3) phase jitter rms (notes 18 and 19) f = 100 mhz, 25 mhz crystal input evaluation band: 0 hz ? nyquist (clock frequency/2) ssoff 0.35 0.7 1.0 ps sson ( ? 0.5%) 0.55 0.8 15. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the d evice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. 16. peak ? to ? peak jitter after applying system transfer function for the common clock architecture. maximum limit for pci express gen 1 is 86 ps peak ? to ? peak for a sample size of 10 6 clock periods. 17. rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture an d reporting the worst case results for each evaluation band. maximum limit for pci express generation 2 is 3.1 ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). 18. rms jitter after applying system transfer function for the common clock architecture. 19. measurement taken from differential output on single ? ended channel terminated with r s = 33.2 , r l = 50 , with test load capacitance of 2 pf and current biasing resistor set at 475 . see figure 5. this parameter is guaranteed by characterization. not tested in production.
nb3n51034 http://onsemi.com 6 phase noise figure 3. typical phase noise at 100 mhz; integration range 12 khz to 20 mhz (input source at 25 mhz and hcsl output termination) figure 4. typical phase noise at 200 mhz; integration range 12 khz to 20 mhz (input source at 25 mhz and hcsl output termination) offset frequency (hz) offset frequency (hz) noise poweer (dbc/hz) noise poweer (dbc/hz)
nb3n51034 http://onsemi.com 7 hcsl interface figure 5. typical termination for hcsl output driver and device evaluation z o = 50 z o = 50 r l = 50 r l = 50 r l * = 33.2 r l * = 33.2 nb3n51034 receiver clk0 clk0 z o = 50 z o = 50 r l = 50 r l = 50 r l * = 33.2 r l * = 33.2 clk3 clk3 *optional r ref = 475 iref lvds compatible interface figure 6. typical termination for lvds device load z o = 50 z o = 50 r l = 150 r l = 150 nb3n51034 receiver clk0 clk0 z o = 50 z o = 50 r l = 150 r l = 150 clk3 clk3 100 100 100 100 lvds device load r ref = 475 iref r l * = 33.2 r l * = 33.2 r l * = 33.2 r l * = 33.2 *optional figure 7. hcsl output parameter characteristics t r t f 525 mv 175 mv 525 mv 175 mv 700 mv 0 mv
nb3n51034 http://onsemi.com 8 ordering information device package shipping ? nb3n51034dtg tssop ? 20 (pb ? free) 75 units / rail NB3N51034DTR2G tssop ? 20 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb3n51034 http://onsemi.com 9 package dimensions tssop ? 20 case 948e ? 02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nb3n51034/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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